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互联网MAC层CRC32 Check Verilog 代码

//////////////////////////////////////////////////////////////////////////////////
// Module Name: eth_mac_rx
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module CRC_chk(
    input           clk,

    input  [7:0]    crc_data,
    input           crc_init,
    input           crc_en,

    input           crc_chk_en,
    output  reg     crc_err,
    
    input           rst
);
//=======================================================================   
//internal signals
//=======================================================================   
reg [31:0]  crc_reg;
//=======================================================================   
//input data width is 8bit, and the first bit is bit[0]
function    [31:0]  nextcrc;
    input   [7:0]   d;
    input   [31:0]  c;
    reg [31:0]      newcrc;
begin
    newcrc[0] = c[24]^c[30]^d[1]^d[7];
    newcrc[1] = c[25]^c[31]^d[0]^d[6]^c[24]^c[30]^d[1]^d[7];
    newcrc[2] = c[26]^d[5]^c[25]^c[31]^d[0]^d[6]^c[24]^c[30]^d[1]^d[7];
    newcrc[3] = c[27]^d[4]^c[26]^d[5]^c[25]^c[31]^d[0]^d[6];
    newcrc[4] = c[28]^d[3]^c[27]^d[4]^c[26]^d[5]^c[24]^c[30]^d[1]^d[7];
    newcrc[5] = c[29]^d[2]^c[28]^d[3]^c[27]^d[4]^c[25]^c[31]^d[0]^d[6]^c[24]^c[30]^d[1]^d[7];
    newcrc[6] = c[30]^d[1]^c[29]^d[2]^c[28]^d[3]^c[26]^d[5]^c[25]^c[31]^d[0]^d[6];
    newcrc[7] = c[31]^d[0]^c[29]^d[2]^c[27]^d[4]^c[26]^d[5]^c[24]^d[7];
    newcrc[8] = c[0]^c[28]^d[3]^c[27]^d[4]^c[25]^d[6]^c[24]^d[7];
    newcrc[9] = c[1]^c[29]^d[2]^c[28]^d[3]^c[26]^d[5]^c[25]^d[6];
    newcrc[10] = c[2]^c[29]^d[2]^c[27]^d[4]^c[26]^d[5]^c[24]^d[7];
    newcrc[11] = c[3]^c[28]^d[3]^c[27]^d[4]^c[25]^d[6]^c[24]^d[7];
    newcrc[12] = c[4]^c[29]^d[2]^c[28]^d[3]^c[26]^d[5]^c[25]^d[6]^c[24]^c[30]^d[1]^d[7];
    newcrc[13] = c[5]^c[30]^d[1]^c[29]^d[2]^c[27]^d[4]^c[26]^d[5]^c[25]^c[31]^d[0]^d[6];
    newcrc[14] = c[6]^c[31]^d[0]^c[30]^d[1]^c[28]^d[3]^c[27]^d[4]^c[26]^d[5];
    newcrc[15] = c[7]^c[31]^d[0]^c[29]^d[2]^c[28]^d[3]^c[27]^d[4];
    newcrc[16] = c[8]^c[29]^d[2]^c[28]^d[3]^c[24]^d[7];
    newcrc[17] = c[9]^c[30]^d[1]^c[29]^d[2]^c[25]^d[6];
    newcrc[18] = c[10]^c[31]^d[0]^c[30]^d[1]^c[26]^d[5];
    newcrc[19] = c[11]^c[31]^d[0]^c[27]^d[4];
    newcrc[20] = c[12]^c[28]^d[3];
    newcrc[21] = c[13]^c[29]^d[2];
    newcrc[22] = c[14]^c[24]^d[7];
    newcrc[23] = c[15]^c[25]^d[6]^c[24]^c[30]^d[1]^d[7];
    newcrc[24] = c[16]^c[26]^d[5]^c[25]^c[31]^d[0]^d[6];
    newcrc[25] = c[17]^c[27]^d[4]^c[26]^d[5];
    newcrc[26] = c[18]^c[28]^d[3]^c[27]^d[4]^c[24]^c[30]^d[1]^d[7];
    newcrc[27] = c[19]^c[29]^d[2]^c[28]^d[3]^c[25]^c[31]^d[0]^d[6];
    newcrc[28] = c[20]^c[30]^d[1]^c[29]^d[2]^c[26]^d[5];
    newcrc[29] = c[21]^c[31]^d[0]^c[30]^d[1]^c[27]^d[4];
    newcrc[30] = c[22]^c[31]^d[0]^c[28]^d[3];
    newcrc[31] = c[23]^c[29]^d[2];
    nextcrc = newcrc;
end
endfunction

always @ (posedge clk or posedge rst)
if (rst)            crc_reg <= 32'hffffffff;
else if (crc_init)  crc_reg <= 32'hffffffff;
else if (crc_en)    crc_reg <= nextcrc(crc_data,crc_reg);

always @ (posedge clk or posedge rst)
if(rst) crc_err <= 0;
else crc_err <= crc_chk_en & (crc_reg[7:0] != 0);
//=======================================================================   

endmodule

 

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